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mosel vitelic 1 v29c51000t/v29c51000b 512k bit (65,536 x 8 bit) 5 volt cmos flash memory preliminary v29c51000t/v29c51000b rev. 0.5 october 2000 features 64kx8-bit organization address access time: 45, 70, 90 ns single 5v 10% power supply sector erase mode operation 8kb boot block (lockable) 512 bytes per sector, 128 sectors sector-erase cycle time: 10ms (max) byte-program cycle time: 20 s (max) minimum 10,000 erase-program cycles low power dissipation active read current: 20ma (typ) active program current: 30ma (typ) standby current: 100 a (max) hardware data protection low v cc program inhibit below 3.2v self-timed program/erase operations with end- of-cycle detection data polling toggle bit cmos and ttl interface available in two versions v29c51000t (top boot block) v29c51000b (bottom boot block) packages: 32-pin plastic dip 32-pin tsop-i 32-pin plcc description the v29c51000t/v29c51000b is a high speed 65,536 x 8 bit cmos flash memory. programming or erasing the device is done with a single 5 volt power supply. the device has separate chip enable ce, program enable we , and output enable oe controls to eliminate bus contention. the v29c51000t/v29c51000b offers a combi- nation of features: boot block with sector erase mode. the end of program/erase cycle is detected by data polling of i/o 7 or by the toggle bit i/o 6 . the v29c51000t/v29c51000b features a sector erase operation which allows each sector to be erased and reprogrammed without affecting data stored in other sectors. the device also supports full chip erase. boot block architecture enables the device to boot from either the top (v29c51000t) or bottom (v29c51000b) sector. all inputs and outputs are cmos and ttl compatible. the v29c51000t/v29c51000b is ideal for applications that require updatable code and data storage. device usage chart operating temperature range package outline access time (ns) temperature mark p t j 457090 0 c to 70 c blank
2 mosel vitelic v29c51000t/v29c51000b v29c51000t/v29c51000b rev. 0.5 october 2000 operating voltage 51: 5v device speed 51000-01 v 29 c 000 51 boot block location t: top b: bottom t 45: 45ns 70: 70ns 90: 90ns blank (0 c to 70 c) p = pdip t = tsop-i j = plcc temp. pkg. pin configurations n/c n/c a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 gnd 1 2 3 4 5 6 8 9 10 11 12 13 14 15 16 30 31 32 29 28 27 26 25 7 24 23 22 21 20 32-pin pdip top view v cc we nc a14 a13 a8 a9 a11 oe a10 ce i/o3 i/o4 i/o5 i/o6 i/o7 19 18 17 51001-02 pin names a 0 a 15 address inputs i/o 0 i/o 7 data input/output ce chip enable oe output enable we program enable v cc 5v 10% power supply gnd ground nc no connect a 6 a 5 a 4 a 3 a 2 a 1 i/o 0 5 6 7 8 9 10 11 12 13 29 51001-03 28 27 26 25 24 23 22 21 a 12 a 15 nc nc v cc we nc a 0 14 i/o 2 gnd i/o 3 i/o 4 i/o 5 i/o 6 a 7 a 13 a 8 a 9 a 11 oe a 10 i/o 7 ce a 14 i/o 1 32 pin plcc top view 15 16 17 18 19 20 4 3 2 1 32 31 30 a11 a9 a8 a13 a14 nc we v cc n/c n/c a15 a12 a7 a6 a5 a4 1 2 3 4 5 6 8 9 10 11 12 13 14 15 16 30 31 32 29 28 27 26 25 7 24 23 22 21 20 32-pin tsop i standard pinout top view oe a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 gnd i/o2 i/o1 a3 a2 a1 a0 i/o0 19 18 17 51001-04
mosel vitelic v29c51000t/v29c51000b 3 v29c51000t/v29c51000b rev. 0.5 october 2000 functional block diagram capacitance (1,2) note: 1. capacitance is sampled and not 100% tested. 2. t a = 25 c, v cc = 5v 10%, f = 1 mhz. latch up characteristics (1) note: 1. includes all pins except v cc . test conditions: v cc = 5v, one pin at a time. ac test load symbol parameter test msetup typ. max. units c in input capacitance v in = 0 6 8 pf c out output capacitance v out = 0 8 12 pf c in2 control pin capacitance v in = 0 8 10 pf parameter min. max. unit input voltage with respect to gnd on a 9 , oe -1 +13 v input voltage with respect to gnd on i/o, address or control pins -1 v cc + 1 v v cc current -100 +100 ma address buffer & latches a 0 a 15 51001-05 i/o buffer & data latches i/o 0 i/o 7 y-decoder 65,536 bit memory cell array x-decoder control logic ce oe we 51001-06 in3064 or equivalent in3064 or equivalent 2.7 k ? 6.2 k ? +5.0 v in3064 or equivalent in3064 or equivalent c l = 100 pf device under test
4 mosel vitelic v29c51000t/v29c51000b v29c51000t/v29c51000b rev. 0.5 october 2000 absolute maximum ratings (1) note: 1. stress greater than those listed unders absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational se ctions of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliabilit y. 2. no more than one output maybe shorted at a time and not exceeding one second long. dc electrical characteristics (over the commercial operating range) symbol parameter commercial unit v in input voltage (input or i/o pins) -2 to +7 v v in input voltage (a 9 pin, oe ) -2 to +13 v v cc power supply voltage -0.5 to +5.5 v t stg storage temerpature (plastic) -65 to +125 c t opr operating temperature 0 to +70 c i out short circuit current (2) 200 (max.) ma parameter name parameter test conditions min. max. unit v il input low voltage v cc = v cc min. 0.8 v v ih input high voltage v cc = v cc max. 2 v i il input leakage current v in = gnd to v cc , v cc = v cc max. 1 a i ol output leakage current v out = gnd to v cc , v cc = v cc max. 1 a v ol output low voltage v cc = v cc min., i ol = 2.1ma 0.4 v v oh output high voltage v cc = v cc min, i oh = -400 a 2.4 v i cc1 read current ce = oe = v il , we = v ih , all i/os open, address input = v il /v ih , at f = 1/t rc min., v cc = v cc max. 40 ma i cc2 program current ce = we = vil, oe = v ih , v cc = v cc max. 50 ma i sb ttl standby current ce = oe = we = v ih , v cc = v cc max. 2ma i sb1 cmos standby current ce = oe = we = v cc 0.3v, v cc = v cc max. 100 a v h device id voltage for a 9 ce = oe = v il , we = v ih 11.5 12.5 v i h device id current for a 9 ce = oe = v il , we = v ih , a9 = v h max. 50 a
mosel vitelic v29c51000t/v29c51000b 5 v29c51000t/v29c51000b rev. 0.5 october 2000 ac electrical characteristics (over all temperature ranges) read cycle program (erase/program) cycle parameter name parameter -45 -70 -90 unit min. max. min. max. min. max. t rc read cycle time 45 70 90 ns t aa address access time 45 70 90 ns t acs chip enable access time 45 70 90 ns t oe output enable access time 25 35 45 ns t clz ce low to output active 0 0 0 ns t olz oe low to output active 0 0 0 ns t df output enable or chip disable to output in high z 020020030ns t oh output hold from address change 0 0 0 ns parameter name parameter -45 -70 -90 unit min. typ. max. min. typ. max. min. typ. max. t wc program cycle time 45 70 90 ns t as address setup time 0 0 0 ns t ah address hold time 35 45 45 ns t cs ce setup time 0 0 0 ns t ch ce hold time 0 0 0 ns t oes oe setup time 0 0 0 ns t oeh oe high hold time 0 0 0 ns t wp we pulse width 25 35 45 ns t wph we pulse width high 20 35 38 ns t ds data setup time 20 25 30 ns t dh data hold time 0 0 0 ns t whwh1 programming cycle 20 20 20 s t whwh2 sector erase cycle 10 10 10 ms t whwh3 chip erase cycle 500 500 500 ms
6 mosel vitelic v29c51000t/v29c51000b v29c51000t/v29c51000b rev. 0.5 october 2000 waveforms of read cycle waveforms of we controlled-program cycle notes: 1. i/o 7 : the output is the complement of the data written to the device. 2. pa: the address of the memory location to be programmed. 3. pd: the data at the byte address to be programmed. t rc t aa t ce t oe t clz t oh t aa t olz t df address ce oe we i/o valid data out valid data out high-z 51000-07 high-z t wc t as pa 5555h t whwh1 t wph t cs t rc t ah t ds t dh t wp t oes t df t oh t oe d out i/o 7 (1) pd (3) a0h 51000-08 address ce oe we i/o 3rd bus cycle pa (2) t ch
mosel vitelic v29c51000t/v29c51000b 7 v29c51000t/v29c51000b rev. 0.5 october 2000 waveforms of ce controlled-program cycle waveforms of erase cycle (1) notes: 1. pa: the address of the memory location to be programmed. 2. pd: the data at the byte address to be programmed. 3. sa: the sector address for sector erase. address = don t care for chip erase. t wc t as t whwh1 t wph t oes t rc t ah t ds t dh t wp t df t oh t oe d out i/o7 pd (2) a0h 51000-09 address 5555h pa pa (1) we oe ce i/o t wc t as t wph address ce oe we i/o 5555h 5555h 5555h 2aaah 2aaah sa aah 55h 80h aah 55h 30h 10h for chip erase 51000-10 t ah t wp t ds t dh t cs
8 mosel vitelic v29c51000t/v29c51000b v29c51000t/v29c51000b rev. 0.5 october 2000 waveforms of data polling cycle waveforms of toggle bit cycle t oeh t ce t whwh1 t oh t df t ch ce oe we i/o 7 i/o 7 i/o 7 valid data out high-z t oe 51000-11 i/o 0 -i/o 6 i/o 0 -i/o 6 invalid valid data out high-z 51000-12 ce we oe t oeh i/o 6
9 v29c51000t/v29c51000b rev. 0.5 october 2000 mosel vitelic v29c51000t/v29c51000b functional description the v29c51000t/v29c51000b consists of 256 equally-sized sectors of 512 bytes each. the 8 kb lockable boot block is intended for storage of the system bios boot code. the boot code is the first piece of code executed each time the system is powered on or rebooted. the v29c51000 is available in two versions: the v29c51000t with the boot block address starting from e000h to ffffh, and the v29c51000b with the boot block address starting from 0000h to ffffh. read cycle a read cycle is performed by holding both ce and oe signals low. data out becomes valid only when these conditions are met. during a read cycle we must be high prior to ce and oe going low. we must remain high during the read operation for the read to complete (see table 1). output disable returning oe or ce high, whichever occurs first will terminate the read operation and place the l/o pins in the high-z state. standby the device will enter standby mode when the ce signal is high. the l/o pins are placed in the high-z, independent of the oe signal. command sequence the v29c51000t/v29c51000b does not provide the reset feature to return the chip to its normal state when an incomplete command sequence or an interruption has happened. in this case, normal operation (read mode) can be restored by issuing a non-existent command sequence, for example address: 5555h, data ffh. byte program cycle the v29c51000t/v29c51000b is programmed on a byte-by-byte basis. the byte program operation is initiated by using a specific four-bus- cycle sequence: two unlock program cycles, a program setup command and program data program cycles (see table 2). during the byte program cycle, addresses are latched on the falling edge of either ce or we , whichever is last. data is latched on the rising edge of ce or we , whichever is first. the byte program cycle can be ce controlled or we controlled. sector erase cycle the v29c51000t/v29c51000b features a sector erase operation which allows each sector to be erased and reprogrammed without affecting data stored in other sectors. sector erase operation is initiated by using a specific six-bus-cycle sequence: two unlock program cycles, a setup command, two additional unlock program cycles, and the sector erase command (see table 2). a sector must be first erased before it can be reprogrammed. while in the internal erase mode, 8kb boot block 512 512 512 512 512 512 8kb boot block v29c51000t v29c51000b ffffh e000h 0000h 1fffh 51000-13 0000h 8kb boot block = 16 sectors table 1. operation modes decoding notes: 1. x = don t care, v ih = high, v il = low. 2. pd: the data at the byte address to be programmed. decoding mode ce oe we a 0 a 1 a 9 i/o read v il v il v ih a 0 a 1 a 9 read program v il v ih v il a 0 a 1 a 9 pd standby v ih xxxxx high-z autoselect device id v il v il v ih v ih v il v h code autoselect manufacture id v il v il v ih v il v il v h code output disable v il v ih v ih x x x high-z
10 mosel vitelic v29c51000t/v29c51000b v29c51000t/v29c51000b rev. 0.5 october 2000 the device ignores any program attempt into the device. the internal erase completion can be determined via data polling or toggle bit. the v29c51000t/v29c51000b is shipped with pre-erased sectors (all bits = 1). chip erase cycle the v29c51000t/v29c51000b features a chip- erase operation. the chip erase operation is initiated by using a specific six-bus-cycle sequence: two unlock program cycles, a setup command, two additional unlock program cycles, and the chip erase command (see table 2). the chip erase operation is performed sequentially, one sector at a time. when the automated on chip erase algorithm is requested with the chip erase command sequence, the device automatically programs and verifies the entire memory array for an all zero pattern prior to erasure the automatic erase begins on the rising edge of the last we or ce pulse in the command sequence and terminates when the data on dq7 is 1 . program cycle status detection there are two methods for determining the state of the v29c51000t/v29c51000b during a program (erase/program) cycle: data polling (i/o 7 ) and toggle bit (i/o 6 ). data polling (i/o 7 ) the v29c51000t/v29c51000b features data polling to indicate the end of a program cycle. when the device is in the program cycle, any attempt to read the device will received the complement of the loaded data on i/o 7 . once the program cycle is completed, i/o 7 will show true data, and the device is then ready for the next cycle. toggle bit (i/o 6 ) the v29c51000t/v29c51000b also features another method for determining the end of a program cycle. when the device is in the program cycle, any attempt to read the device will result in l/o 6 toggling between 1 and 0. once the program is completed, the toggling will stop. the device is then ready for the next operation. examining the toggle bit may begin at any time during a program cycle. boot block protection the v29c51000t/v29c51000b features hardware boot block protection. this feature will prevent erasing/programming of data in the boot block once the feature is enabled (see table 3). the device is shipped with the boot block unprotected. autoselect the v29c51000t/v29c51000b features an autoselect mode to identify the boot block (protected/unprotected), the device (top/bottom), and the manufacturer id. to get to the autoselect mode, a high voltage (v h ) must be applied to the a 9 pin. once the a 9 signal is returned to low or high, the device will return to the previous mode. table 2. command codes notes: 1. top boot sector 2. bottom boot sector 3. pa: the address of the memory location to be programmed. 4. pd: the data at the byte address to be programmed. command sequence first bus program cycle second bus program cycle third bus program cycle fourth bus program cycle fifth bus program cycle six bus program cycle address data address data address data address data address data address data read xxxxh f0h read 5555h aah 2aaah 55h 5555h f0h ra rd autoselect 5555h aah 2aaah 55h 5555h 90h 00h 40h 01h 00h (1) a0h (2) byte program 5555h aah 2aaah 55h 5555h a0h pa pd(4) chip erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h 5555h 10h sector erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h pa(3) 30h
11 v29c51000t/v29c51000b rev. 0.5 october 2000 mosel vitelic v29c51000t/v29c51000b boot block detection in autoselect mode, performing a read at address 3cxx2h or address 0cxx2h will indicate if the top boot block sector or the bottom boot block sector is locked out. if the data is 01h, the top/bottom boot block is protected. if the data is 00h, the top/bottom boot block is unprotected. (see table 3.) device id in autoselect mode, performing a read at address xxxxh will determine whether the device is a top boot block device or a bottom boot block device. if the data is 00h, the device is a top boot block. if the data is a0h, the device is a bottom boot block device (see table 3). in addition, the device id can also be read via the command register when the device is erased or programmed in a system without applying high voltage to the a 9 pin. when a 0 is high, the device id is presented at the outputs. manufacturer id in autoselect mode, performing a read at address. xxxx0h will determine the manufacturer id. 40h is the manufacturer code for mosel vitelic flash. in addition the manufacturer id can also be read via the command register when the device is erased or programmed in a system without applying high voltage to the a 9 pin. when a 0 is low, the manufacturer id is presented at the outputs. hardware data protection v cc sense protection: the program operation is inhibited when vcc is less than 2.5v. noise protection: a ce or we pulse of less than 5ns will not initiate a program cycle. program inhibit protection: holding any one of oe low, ce high or we high inhibits a program cycle. table 3. autoselect decoding note: 1. x = don t care, v ih = high, v il = low. decoding mode boot block address data i/o 0 i/o 7 a 0 a 1 a 2 a 13 a 14 a 17 boot block protection top v il v ih xv ih 01h: protected bottom v il v ih xv il 00h: unprotected device id top v ih v il x x 01h bottom 00h manufacture id v il v il x x a0h
12 mosel vitelic v29c51000t/v29c51000b v29c51000t/v29c51000b rev. 0.5 october 2000 byte program algorithm chip/sector erase algorithm write program command sequence add/data 5555h/aah 2aaah/55h 5555h/a0h four bus cycle sequence pa/pd data polling (i/o7) or toggle bit (i/o6) programming completed verify byte? yes no write erase command sequence add/data 5555h/aah 2aaah/55h 5555h/80h six bus cycle sequence 5555h/aah 2aaah/55h 5555h/10h (chip erase) pa/30h (sector erase data polling or toggle bit successfully completed erase complete 51000-14
mosel vitelic v29c51000t/v29c51000b 13 v29c51000t/v29c51000b rev. 0.5 october 2000 data polling algorithm toggle bit algorithm note: 1. pba: the byte address to be programmed. read i/o 7 address = pba (1) program done program done i/o 7 = data no yes read i/o 6 no yes i/o 6 toggle read i/o 6 51000-15
14 mosel vitelic v29c51000t/v29c51000b v29c51000t/v29c51000b rev. 0.5 october 2000 package diagrams 32-pin plastic dip 32-pin plcc 15 max 0.545/0.555 index-1 .047 +.012 0 0.210 max 0.120 min 0.010 min .600 typ 1.660 max. .050 max .100 typ .032 +.012 0 .018 +.006 .002 .010 +.004 .0004 index-2 ejector mark .420 .003 3 - 6 3 - 6 3 - 6 .017 30 .136 .003 .110 .046 .003 .025 .050 typ .450 .003 .490 .005 .045x45 .590 .005 .550 .003 20 19 18 17 16 15 14 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 13 12 11 10 9 8 7 6 5
mosel vitelic v29c51000t/v29c51000b 15 v29c51000t/v29c51000b rev. 0.5 october 2000 32-pin tsop-i 0.032 typ. 0.020 sbc 0.003 max 0.020 max. 0.024 0.004 seating plane 0.010 see detail a detail a 0.724 typ. (0.728 max.) 0.787 0.008 0.009 0.002 0.315 typ. (0.319 max.) 0.035 0.002 0.047 max. 0.005 min. 0.007 max. units in inches
mosel vitelic worldwide offices v29c51000t/v29c51000b mosel vitelic 3910 n. first street, san jose, ca 95134-1501 ph: (408) 433-6000 fax: (408) 433-0952 tlx: 371-9461 the information in this document is subject to change without notice. mosel vitelic makes no commitment to update or keep cur- rent the information contained in this document. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of mosel-vitelic. mosel vitelic subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applica- tions. mosel vitelic does not do testing appropriate to provide 100% product quality assurance and does not assume any liabil- ity for consequential or incidental arising from any use of its prod- ucts. if such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. ? copyright 2000, mosel vitelic inc. 10/00 printed in u.s.a. u.s. sales offices u.s.a. 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-0952 hong kong 19 dai fu street taipo industrial estate taipo, nt, hong kong phone: 852-2666-3307 fax: 852-2770-8011 taiwan 7f, no. 102 min-chuan e. road, sec. 3 taipei phone: 886-2-2545-1213 fax: 886-2-2545-1209 no 19 li hsin road science based ind. park hsin chu, taiwan, r.o.c. phone: 886-3-579-5888 fax: 886-3-566-5888 singapore 10 anson road #23-13 international plaza singapore 079903 phone: 65-3231801 fax: 65-3237013 japan onze 1852 building 6f 2-14-6 shintomi, chuo-ku tokyo 104-0041 phone: 03-3537-1400 fax: 03-3537-1402 uk & ireland suite 50, grovewood business centre strathclyde business park bellshill, lanarkshire, scotland, ml4 3nq phone: 44-1698-748515 fax: 44-1698-748516 germany (continental europe & israel) benzstrasse 32 71083 herrenberg germany phone: +49 7032 2796-0 fax: +49 7032 2796 22 northwestern 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-0952 southwestern 302 n. el camino real #200 san clemente, ca 92672 phone: 949-361-7873 fax: 949-361-7807 central, northeastern & southeastern 604 fieldwood circle richardson, tx 75081 phone: 972-690-1402 fax: 972-690-0341

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